# HG changeset patch
# User Petri Hintukainen <phintuka@users.sourceforge.net>
# Date 1177780535 -10800
# Node ID 868a133a04b6ca8b5893d46add1e0c58e9890777
# Parent  a36c1bebf8fdee91e75ed07cbd4e2d33554c660b
Add acceleration flags for SSE3 and SSSE3

diff -r a36c1bebf8fd -r 868a133a04b6 src/xine-utils/xineutils.h
--- a/src/xine-utils/xineutils.h	Fri Apr 27 15:48:21 2007 +0300
+++ b/src/xine-utils/xineutils.h	Sat Apr 28 20:15:35 2007 +0300
@@ -111,6 +111,8 @@ extern "C" {
 #define MM_ACCEL_X86_MMXEXT     0x20000000
 #define MM_ACCEL_X86_SSE        0x10000000
 #define MM_ACCEL_X86_SSE2       0x08000000
+#define MM_ACCEL_X86_SSE3       0x00400000
+#define MM_ACCEL_X86_SSSE3      0x00200000
 
 /* powerpc accelerations and features */
 #define MM_ACCEL_PPC_ALTIVEC    0x04000000
# HG changeset patch
# User Petri Hintukainen <phintuka@users.sourceforge.net>
# Date 1177780613 -10800
# Node ID 77f0f0afae6b06c1144d7f48e95675e28e4972b3
# Parent  868a133a04b6ca8b5893d46add1e0c58e9890777
Add tests for SSE3 and SSSE3
Implement CPUID check for x86_64
(SSE3 and SSSE3 are not available in every platform)

diff -r 868a133a04b6 -r 77f0f0afae6b src/xine-utils/cpu_accel.c
--- a/src/xine-utils/cpu_accel.c	Sat Apr 28 20:15:35 2007 +0300
+++ b/src/xine-utils/cpu_accel.c	Sat Apr 28 20:16:53 2007 +0300
@@ -56,10 +56,14 @@ static uint32_t arch_accel (void)
   /* No need to test for this on AMD64, we know what the
      platform has.  */
   caps = MM_ACCEL_X86_MMX | MM_ACCEL_X86_SSE | MM_ACCEL_X86_MMXEXT | MM_ACCEL_X86_SSE2;
-#else
+#endif
 
 #ifndef _MSC_VER
+# ifdef __x86_64__
+  uint64_t eax, ebx, ecx, edx;
+#else
   uint32_t eax, ebx, ecx, edx;
+#endif
   int AMD;
 
   caps = 0;
@@ -73,7 +77,20 @@ static uint32_t arch_accel (void)
          : "a" (op)                     \
          : "cc")
 #else   /* PIC version : save ebx */
-#define cpuid(op,eax,ebx,ecx,edx)       \
+# ifdef __x86_64__
+# define cpuid(op,eax,ebx,ecx,edx)      \
+    __asm__ ("push %%rbx\n\t"           \
+         "cpuid\n\t"                    \
+         "mov %%rbx,%1\n\t"             \
+         "pop %%rbx"                    \
+         : "=a" (eax),                  \
+           "=r" (ebx),                  \
+           "=c" (ecx),                  \
+           "=d" (edx)                   \
+         : "a" (op)                     \
+         : "cc")
+# else
+# define cpuid(op,eax,ebx,ecx,edx)      \
     __asm__ ("pushl %%ebx\n\t"          \
          "cpuid\n\t"                    \
          "movl %%ebx,%1\n\t"            \
@@ -84,8 +101,11 @@ static uint32_t arch_accel (void)
            "=d" (edx)                   \
          : "a" (op)                     \
          : "cc")
-#endif
-
+# endif
+#endif
+
+# ifndef __x86_64__
+  /* No need to test for CPUID on AMD64 */
   __asm__ ("pushfl\n\t"
        "pushfl\n\t"
        "popl %0\n\t"
@@ -105,6 +125,7 @@ static uint32_t arch_accel (void)
     /* no cpuid */
     return 0;
   }
+# endif
 
   cpuid (0x00000000, eax, ebx, ecx, edx);
   if (!eax) {
@@ -130,6 +151,18 @@ static uint32_t arch_accel (void)
     caps |= MM_ACCEL_X86_SSE2;
   }
 
+  if(caps & MM_ACCEL_X86_SSE2) {
+    if (ecx & 0x00000001) {
+      /* SSE3 */
+      caps |= MM_ACCEL_X86_SSE3;
+    }
+
+    if (ecx & 0x00000200) {
+      /* SSSE3 */
+      caps |= MM_ACCEL_X86_SSSE3;
+    }
+  }
+
   cpuid (0x80000000, eax, ebx, ecx, edx);
   if (eax >= 0x80000001) {
     cpuid (0x80000001, eax, ebx, ecx, edx);
@@ -147,6 +180,8 @@ static uint32_t arch_accel (void)
 #else
   caps = 0;
 #endif /* _MSC_VER */
+
+#ifndef __x86_64__
 
   /* test OS support for SSE */
   if (caps & MM_ACCEL_X86_SSE) {